1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to complex integrated circuits that comprise metal gate electrode structures formed according to a replacement gate approach.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreased with the introduction of every new circuit generation, to provide currently available integrated circuits with a high performance in terms of speed and/or power consumption. A reduction of the size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
With the increasing shrinkage of the features sizes of semiconductor-based circuit elements such as transistors, thereby significantly increasing the overall complexity of the manufacturing processes, also the complexity of a wiring system that establishes the electrical connection of the semiconductor-based circuit elements and of any other circuit elements has to be adapted to the increasing number of circuit elements and the significantly increased packing density. Consequently, typically, in complex integrated circuits, a plurality of stacked wiring layers or metallization layers are required, in which metal lines and vias commonly establish the electrical connections as required by the circuit layout of the device under consideration. Due to the overall reduced feature sizes, the dimensions of metal lines and vias have also been continuously reduced, thereby requiring new strategies and materials for the complex metallization systems.
For this reason, copper in combination with so-called low-k dielectric materials are typically used in complex metallization systems, which, however, may be associated with significant problems in view of the handling of copper in a semiconductor facility. It is well known that copper readily diffuses in a plurality of materials, such as silicon dioxide, silicon dioxide-based low-k dielectric materials and the like. Copper, when diffusing into sensitive device areas such as complex transistor elements, however, may significantly alter the transistor characteristics and may thus finally result in yield loss and reduced reliability of complex semiconductor devices. Therefore, complex manufacturing strategies have been developed in forming complex metallization systems in which the copper material may typically be provided in combination with appropriate conductive and dielectric barrier materials in order to ensure an appropriate copper confinement. Although generally copper may provide superior electrical performance and improved electromigration behavior compared to a plurality of other materials, such as aluminum and the like, other conductive materials and metals may typically be used so as to connect directly to the semiconductor-based circuit elements in order to avoid the risk of copper diffusion into these semiconductor devices. Moreover, the semiconductor-based circuit elements, such as transistors and the like, may typically require a certain degree of passivation, i.e., a certain mechanical and chemical resistivity, and thus the transistor structures are typically embedded in an appropriate dielectric material which may comprise two or more different material layers, depending on the overall device requirements. The dielectric material for passivating the semiconductor-based circuit elements, which will also be referred to herein as an interlayer dielectric material, may thus represent an appropriate interface between the actual semiconductor-based circuit elements and the complex metallization system, which is frequently comprised of copper and sophisticated low-k dielectric materials. In order to appropriately connect the circuit elements to the metallization system, appropriate contact elements have to be provided in the interlayer dielectric material so as to provide, in some cases, a direct connection between several circuit elements and also provide a connection of contact areas of the circuit elements with metal lines or generally metal regions in the very first metallization layer of the metallization system. The combination of the passivating dielectric material and the contact elements formed therein may also be referred to as a contact structure or contact level of the semiconductor device. Consequently, upon reducing the dimensions of the circuit elements in the device level, a corresponding adaptation of the critical dimensions of the contact elements is required, thereby resulting in very complex patterning regimes for forming the contact elements in the interlayer dielectric material. That is, in densely packed device areas, the critical dimensions of the contact elements may be of the same order of magnitude as the critical dimensions of the circuit elements, thereby also requiring comparable critical dimensions in the very first metallization layer in order to not unduly consume valuable chip area. The contact elements are typically formed by first patterning the interlayer dielectric material using sophisticated lithography and etch techniques and subsequently filling the contact openings with an appropriate conductive material, such as tungsten and the like, possibly in combination with conductive barrier materials, if required. Hence, depending on the thickness of the interlayer dielectric material, the contact openings have to be formed on the basis of very critical process conditions since openings with a lateral dimension of 50 nm and less may have to be formed through an interlayer dielectric material of 150 nm and more, depending on the overall device architecture. After providing the contact openings with the desired critical dimensions, a further critical process step is required, i.e., the deposition of an appropriate conductive material, which is to reliably fill the contact openings without undue irregularities, such as voids within the contact openings and the like, in order to obtain a low contact resistivity. In this respect, it should be appreciated that, in sophisticated applications, the overall signal processing capability may significantly depend on the overall resistance in the device level and in the contact level, wherein, in extremely scaled semiconductor devices, the contact resistivity may be the dominant factor that determines the final electrical performance. After the deposition of the contact material, any excess portion thereof has to be removed, which is typically accomplished on the basis of chemical mechanical polishing (CMP) techniques in which appropriate process parameters, such as downforce, relative speed of the polishing pad and the substrate and, in particular, the chemistry of the slurry material, is appropriately selected so as to efficiently remove the excess material without unduly causing damage in other device areas, such as the dielectric material of the contact level and the like. During the removal process, the conductive material is removed from dielectric surface areas in order to provide electrically insulated contact elements, thereby requiring a certain degree of over-polishing time, which may depend on the overall process uniformity. That is, the over-polish time has to be selected such that the excess material is reliably removed in any device areas, such as densely packed device areas or device areas of reduced packing density. In this phase of the removal process, it is important to avoid undue material removal of the dielectric material, which may be accomplished by using a highly selective slurry material, which may thus provide a chemical reaction with the conductive material without unduly affecting the dielectric material.
The continuous shrinkage of critical dimensions of transistor elements has resulted in a minimum gate length of field effect transistors of 40 nm and less. As is well known, transistors of very short channel length may require additional measures for preserving the controllability of the channel region, which has typically been addressed by reducing the thickness of a gate dielectric material, which separates the gate electrode structure of the field effect transistor from the underlying channel region. Thus, by reducing the thickness of the gate dielectric material, the capacitive coupling between the electrode and the channel region may be increased, thereby enabling, in combination with very complex dopant profiles for the drain and source regions, a proper control of the conductive channel, which forms in the channel region upon application of an appropriate control voltage to the gate electrode. Due to the many advantages in using silicon dioxide as a base material for gate insulation layers formed on a silicon-based channel region, silicon dioxide-based dielectric materials have widely been used as a gate dielectric material. For a thickness of approximately 1.5 nm and below, however, the corresponding gate leakage currents in sophisticated transistors may reach values that are no longer acceptable for many types of complex semiconductor devices. For this reason, new strategies have been developed in which the drain and source regions may be provided in a self-aligned manner, as is the case in well-established polysilicon/silicon dioxide gate electrode structures, while nevertheless increasing the effective thickness of the gate dielectric material while providing an oxide equivalent thickness of 1.5 nm and less. To this end, so-called high-k dielectric materials, i.e., dielectric materials having a dielectric constant of 10.0 and higher, may be incorporated into the gate insulation layer of sophisticated transistors, thereby reducing the leakage currents while nevertheless providing the desired capacitive coupling. Moreover, performance of the gate electrode structures may further be enhanced by replacing the polysilicon material by a metal of superior conductivity, thereby generally reducing the gate resistivity and also avoiding the creation of a depletion zone in the vicinity of the gate dielectric material, as is typically observed in polysilicon-based gate electrode structures.
Providing a high-k dielectric material in combination with a metal-containing electrode material in an early manufacturing stage may result in significant difficulties, for instance for adjusting an appropriate work function and preserving its value throughout the entire process flow. Therefore, in very promising approaches, i.e., so-called replacement gate approaches, the gate electrode structures may be formed with a high degree of compatibility with conventional polysilicon gate electrodes, and the highly conductive electrode metal, possibly in combination with any work function adjusting species and possibly together with a high-k dielectric material, may be provided in a very late manufacturing stage, i.e., after completing the basic transistor structure and laterally embedding the gate electrode structure in the interlayer dielectric material. In this manufacturing stage, an opening or trench may be formed in the gate electrode structure by removing the polysilicon material and any appropriate material system may be filled into the gate opening. For example, highly conductive electrode metals, such as aluminum, may frequently be used in order to obtain a desired low resistivity of the high-k metal gate electrode structures. Thus, at a final stage of this replacement gate approach, the electrode metal has to be deposited and subsequently any excess portion thereof needs to be removed, which may typically be accomplished on the basis of a CMP process. It turns out, however, that in particular the final phase of the replacement gate approach may result in significant defectivity and even device failures upon forming contact elements, as will be explained in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of the semiconductor device 100 in an advanced manufacturing stage. As illustrated, the device 100 comprises a substrate 101 and a semiconductor layer 102, such as a silicon-based semiconductor material and the like. The semiconductor layer 102 and the substrate 101 may represent a silicon-on-insulator (SOI) architecture when a buried insulating material (not shown) is formed below the semi-conductor layer 102. In other cases, the semiconductor layer 102 may represent, at least in an initial manufacturing stage, a portion of a crystalline material of the substrate 101, thereby forming a bulk configuration. A plurality of transistors 150A, 150B are formed in and above the semiconductor layer 102, wherein, in the example shown, a planar transistor architecture may be used. In this case, the transistors 150A, 150B comprise drain and source regions 153 within the semiconductor layer 102 and laterally enclose a channel region 152, in which a conductive channel forms upon applying an appropriate control voltage to a gate electrode structure 130, as is previously explained. The drain and source regions 153 may comprise appropriate contact areas, in the example shown as metal silicide regions 154. In other cases, the contact areas 154 may be highly doped semiconductor regions, which may receive a metal silicide in a later manufacturing stage, for instance after completing the gate electrode structures 130, if any additional high temperature processes are required which are not compatible with the thermal stability of a desired metal silicide material.
The gate electrode structures 130 may initially be provided on the basis of a polysilicon material, which may be patterned on the basis of design requirements in order to adjust a desired critical dimension of the gate electrode structure 130, which may be 40 nm and less in sophisticated applications. In the manufacturing stage shown, the gate electrode structures 130 may be laterally enclosed by a sidewall spacer structure 151 having any appropriate configuration, in combination with a dielectric material 120, which may also be referred to as an interlayer dielectric material and which may comprise two or more individual material layers, such as layers 121, 122, depending on the overall process and device requirements. For example, the layer 121 may represent a silicon nitride-based material, while the layer 122 may comprise silicon dioxide, which is frequently used as a material for embedding semiconductor-based circuit elements of sophisticated semiconductor devices. The gate electrode structures 130 may comprise a gate insulation layer 131, which may comprise a high-k dielectric material, for instance in the form of hafnium oxide, hafnium silicon oxide, zirconium oxide and the like. As illustrated, the gate dielectric material 131 may also be formed on sidewalls of the gate electrode structure 130, while, in other cases, the gate dielectric material may only be formed at the bottom of the gate opening 130O. Moreover, in the example shown, a metal-containing material layer 132, for instance in the form of lanthanum, aluminum and the like, may be provided and may have incorporated therein an appropriate metal species so as to adjust the work function of the gate electrode structure 130. Finally, a highly conductive electrode metal 133, such as aluminum, an aluminum alloy, for instance aluminum titanium, and the like, may be provided so as to act as a low ohmic electrode material.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following process strategy. Appropriate active regions (not shown) may be formed in the semiconductor layer 102 by providing appropriate isolation structures (not shown) in order to laterally delineate the active regions. Thereafter, the gate electrode structures 130 may be formed by providing an appropriate stack of material layers, such as a silicon dioxide layer, a polysilicon layer in combination with further materials, such as a dielectric cap material, hard mask materials and the like, as may be required for the further processing of the device 100. Next, sophisticated lithography and etch techniques may be applied in order to pattern the gate electrode structures 130 similar to conventional process strategies using silicon dioxide/polysilicon gate electrode structures without any sophisticated high-k materials. In other approaches, the high-k dielectric material in combination with a conductive cap material may be provided in this early manufacturing stage together with a silicon material. After the patterning of the gate electrode structures, for instance with a critical length of 40 nm and less, the further processing is continued on the basis of any appropriate process flow for forming the drain and source regions 153 in combination with the sidewall spacer structure 151. After any high temperature processes for activating the dopants and adjusting the final dopant profile of the drain and source regions 153, the metal silicide 154 may be formed on the basis of any appropriate silicidation technique. Next, the material 120 may be formed, for instance by depositing the layers 121, 122, which may include the deposition of highly stressed dielectric materials for further enhancing performance of one or both of the transistors 150A, 150B and the like. Thereafter, the material 120 may be planarized so as to finally expose the polysilicon material in the gate electrode structures 130, which may then be removed on the basis of highly selective etch chemistries, thereby forming the gate openings 130O. It should be appreciated that also any dielectric material provided at the bottom of the gate opening 130O may be removed, at least partially, if considered appropriate, and thereafter the high-k dielectric material 131 may be deposited. In other cases, a high-k dielectric material may have been provided in an early manufacturing stage. If required, the material layer 132 is deposited by any appropriate deposition technique, followed by the deposition of the electrode metal 133, which may be accomplished by sputter deposition, electrochemical deposition and the like. In order to reliably fill the gate openings 130O, a certain degree of overfill is typically required, as is shown in dashed lines in FIG. 1a. Next, any excess material of the layer 133 and possibly of the layer 132 is removed on the basis of a chemical mechanical polishing process 103, in which preferably the material of the layer 133 is removed. As discussed above, typically, an appropriate slurry material, i.e., a solution including an appropriate chemically active component, is applied, while abrasives may also be provided in order to provide a significant physical component in removing the materials 133 and 132. For example, when removing aluminum material or aluminum alloys, typically alumina, i.e., aluminum oxide, may be used as an appropriate material for the abrasive particles, which, however, tend to agglomerate, in particular at a final phase of the removal process 103, when typically two different metal species, such as the material of the layer 133 and the metal component of the layer 132, are to be polished. Consequently, in addition to any micro scratches, which may be caused by the alumina particles in the dielectric material 120, i.e., after removing the very thin dielectric material 131, if provided at all, the increasing agglomeration of the alumina particles may cause pronounced cracks in the material 122, as indicated by 124. Since a corresponding over-polish time may have to be applied in order to reliably remove any metal residues, a significant number of cracks 124 may be generated during the removal process 103.
After the removal process 103, the gate electrode structures 130 are laterally embedded by the interlayer dielectric material 120, while, on the other hand, the highly conductive gate electrode structures 130 have exposed metal surface areas, thereby allowing contact by any metal regions of a metallization system. On the other hand, the contact areas 154 in the drain and source regions 153 may require contact elements extending through the interlayer dielectric material 120, wherein, however, contrary to many other conventional approaches, these contact elements may be formed through a moderately thin dielectric material, thereby avoiding undue aspect ratio and thus allowing the patterning of contact openings with reduced lateral dimensions.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. An etch mask 104, such as a resist mask and the like, is formed on the interlayer dielectric material 120 and is appropriately configured so as to define the lateral size and position of contact openings 123 to be formed in the material 120. Since the height of the contact openings 123 is substantially restricted to the height of the gate electrode structures 130, desired reduced lateral dimensions may be achieved, thereby enabling providing the semiconductor device 100 with an increased packing density. That is, the lateral offset of the transistors 150A, 150B may be selected so as to comply with the patterning capability for forming the contact opening 123 through the layer 120 having a height that substantially corresponds to the height of the gate electrode structures 130. The etch mask 104 may be provided on the basis of any appropriate lithography technique. Thereafter, an appropriate etch sequence is applied so as to etch through the materials 122 and 121 in order to finally expose the metal silicide in the contact areas 154. Thereafter, the etch mask 104 is removed and, if required, appropriate cleaning processes may be applied.
FIG. 1c schematically illustrates a top view of the semiconductor device 100 after the above-described process sequence. As illustrated, a plurality of the gate electrode structures 130 is provided and the contact openings 123 are appropriately positioned so as to provide the required electrical contact to the transistors 150A, 150B, as shown in FIGS. 1a and 1b. Furthermore, as shown, the cracks 124 may be present in a more or less pronounced degree, wherein some of the cracks 124 may extend between two contact openings 123, as is illustrated at the left hand side in FIG. 1c. 
FIG. 1d schematically illustrates the device 100, again in a cross-sectional view, in a further advanced manufacturing stage. As illustrated, a contact material 126, possibly in combination with a conductive barrier material 127, is formed above the dielectric material 120 and within the contact openings 123. For example, the contact material 126 may be comprised of tungsten, while the conductive barrier material 127 may comprise titanium, titanium nitride and the like. The materials 126, 127 may be provided on the basis of any appropriate deposition technique, such as chemical vapor deposition (CVD) and the like.
FIG. 1e schematically illustrates the device 100 during a further removal process 105 that comprises a chemical mechanical polishing process. During the process 105, any excess material of the layers 126 and 127, if provided, (FIG. 1d) are removed as discussed above. Typically, a specific slurry material may have to be selected so as to provide a desired degree of selectivity during the polishing process 105. During a final phase of the process 105, however, at least two different metals may be present, i.e., the electrode metal 133, such as aluminum, an aluminum alloy and the like, and the contact material 126, for instance in the form of tungsten. Consequently, due to different electrochemical behavior of the metals 133, 126, these materials may respond differently to the slurry used, which may result in a different degree of material removal in the final phase of the process 105. In some cases, metal agglomeration may be observed in one type of metal, while a pronounced metal depletion may be observed for the other type of metal during the final polishing phase. Furthermore, since a certain over-polish time may have to be applied in order to provide electrically insulated contact elements 125, a corresponding difference in response to the applied slurry material may thus result in metal depletion, for instance in the contact elements 125. On the other hand, the previously generated cracks 124 may still remain filled with the contact material, thereby providing efficient leakage paths.
FIG. 1f schematically illustrates the semiconductor device 100 after the polishing process 105 shown in FIG. 1e. As illustrated, some of the contact elements 125 may include irregularities, such as depleted zones 125A, which may result in a significantly increased contact resistivity. On the other hand, metal-filled cracks, such as the crack 124 on the left hand side of FIG. 1f, may connect two of the contact elements 125 thereby short-circuiting these contacts 125, which may even result in a total failure of the device 100.
Consequently, in a contact regime using the dielectric material 120 for forming contact elements of reduced height, the conventional strategy described above may provide significant defectivity and device failures, which may thus contribute to a reduced production yield. In some conventional approaches, superior slurry materials may be used during the removal process 105 of FIG. 1e which, however, may require significant research and development efforts for obtaining an appropriate chemical solution, while nevertheless a desired balance between the chemical response of two different metal materials may nevertheless be very difficult to achieve. Moreover, the metal-filled cracks may nevertheless contribute to significant contact failures.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.